1. Field of the Invention
The present invention relates to a scan test method, an integrated circuit, and a scan test circuit.
2. Description of Related Art
A scan test is a technique to test an integrated circuit to detect defects. The scan test requires a scan chain placed in the integrated circuit. The scan chain includes flip-flops connected in series to form a shift register.
A combinational circuit has its output determined entirely by concurrent inputs. Thus, the presence of defects in the combinational circuit can be detected as follows. First, an input is applied to the combinational circuit, and the output of the combinational circuit is provided to the flip-flops by capture operation. The captured values are then output serially by the scan chain and compared with an expected value. From the comparison result, the presence or absence of defects in the combinational circuit is determined.
Referring first to FIGS. 5 and 6, a conventional integrated circuit (IC) 100 having a scan test function includes combinational circuits 101a, 101b, 101c, and flip-flops 111, 112, 113, 114. The flip-flops 111 to 114 are placed between the combinational circuits. The flip-flops 111 to 114 are connected in series with each other to serve as a shift register, thereby forming a scan chain 110.
Each of the flip-flops 111 to 114 is a scan cell having a multiplexer (not shown). The multiplexer allows switching a shift register operation mode and a capture operation mode. In the capture operation mode, values pass through the combinational circuits. The multiplexer selects the output of the combinational circuit in the normal operation mode and selects the output of the flip-flop of the previous stage in the shift register operation mode. The multiplexer then inputs the selected output to the flip-flop of the next stage.
FIG. 5 schematically shows a conventional IC in the shift register operation mode. FIG. 6 schematically shows the conventional IC in the capture operation mode.
For simplification, FIGS. 5 and 6 show only one scan chain, four flip-flops forming the scan chain, and three combinational circuits. An actual circuit, however, includes more flip-flops and combination circuits in the left side of the combination circuit 101a and in the right side of the combination circuit 101c of FIGS. 5 and 6. The number of scan chains and flip-flops forming each scan chain depend on the size of the IC 100.
The scan test of the IC 100 is explained below with reference to FIG. 7.
Initialization (S101)
Initially in the scan test process, the IC 100 is set in the mode shown in FIG. 5. A test value of “1” or “0” is set to all the flip-flops forming the scan chain 110. For example, the values “1”, “1”, “1”, “1” are set to the flip-flops 111 to 114. These values are serially input to the flip-flops 111 to 114 of the scan chain 110 from an input terminal 110a of the scan chain 110 in synchronization with a clock signal input to the flip-flops 111 to 114 from a clock input terminal (not shown). This operation, called the shift operation, is repeated the number of stages of the flip-flops 111 to 114 forming the scan chain 110, thereby setting the values to all the flip-flops 111 to 114.
Capture Operation (S102)
Next, the IC 100 is set in the capture operation mode shown in FIG. 6. The values of the flip-flops 111 to 114 set in the previous step S101 are captured by other flip-flops through the combinational circuits 101a to 101c. The values of the flip-flops 111 to 114 are thereby updated. The capture operation is unidirectional in the direction of the arrow B in FIG. 6.
Output, Comparison, and Reset (S103)
Then, the IC 100 is set in the shift register operation mode again. The values of the flip-flops 111 to 114 are output from an output terminal 110b of the scan chain 110. These output values are compared with an expected value to see if they match. In parallel with the output, next values are input to the flip-flops 111 to 114 of the scan chain 110 to reset them. The next values are different from the values input previously. In this case, since the values “1”, “1”, “1”, “1” have been input initially, the values “1”, “1”, “1”, “0”, for example, are input in this step. The values of the flip-flops 111 to 114 are thereby updated.
The steps S102 to S103 are repeated the number of times required to detect defects in all the part of the combinational circuits 101a to 101c. The process determines if the repeat number reaches a preset number in the step S104 in FIG. 7. If not, the process repeats from S102, and, if so, the process ends.
If any comparison result of a plurality of comparisons shows that the output value is different from the expected value, the IC 100 is determined to be defective. If it shows that all the output values are the same as the expected value, the IC 100 is determined to be non-defective.
The expected value is a value to be output if the IC 100 is non-defective. This value is calculated by simulation based on input values and the configuration of the combinational circuits.
Another conventional scan test method is described in Japanese Unexamined Patent Application Publication No. 05-134007 (Yamashita) and illustrated in FIGS. 1 and 2. This technique feeds the output of a scan chain through a logic circuit L1 in FIG. 1 or L2 in FIG. 2 back to an input terminal of the scan chain for re-input, thereby compressing the data of a test pattern, which is a test vector for scan pass in this art. Since this technique inverts the re-input value to a specific flip-flop by the logic circuit L1 or L2, it allows update and reset of the value of each flip-flop without input of a new test pattern.
In the IC 100 shown in FIGS. 5 and 6, if the number of times to perform the capture operations is “m”, the number of flip-flops of the scan chain 110 corresponding to the number of clocks required for serial data input by the scan pass is “n”, and the number of clocks required for one capture operation is “c”, the number of test patterns (clocks) required is given by:m*(n+c)+n  (1)where the values of “m”, “n”, and “c” are positive integers. For example, the value “m” is 3000 to 10000, “n” is 10000 to 200000, and “c” is 1. This means that the value of “n” is the most critical for the test pattern number.
The present invention has recognized that, it is necessary in the IC 100 to input a new value from the input terminal of the scan chain to set it to the flip-flops each time the capture operation is performed. This requires a large number of test patterns (clocks) and takes a long test time. Further, it is necessary to store all the input values supplied each time, requiring a large memory capacity. Furthermore, since the output of the scan chain is compared with the expected value in each capture operation, it is necessary to store a large number of expected values for comparison, also requiring a large memory capacity. In addition, the comparison takes a long time to process a large amount of data.
The present invention has also recognized that, the technique taught by Yamashita requires the logic circuit L1 or L2 for inverting the re-input value to a specific flip-flop. It further requires data for determining a signal, “1” or “0”, to be input to an input terminal DAT1 (or DAT2) of the logic circuit L1 (or L2) from test vector memory MEM1 (or MEM2). This inhibits the reduction of the amount of data required.